Intel has confirmed plans to ship processors built from a 45nm fabrication process in the second half of 2007. The first family of chips, codenamed Penryn, will have higher clock speeds than current processors while staying within the same power envelope, the company said.

Penryn chips represent the second generation of Intel's Core microarchitecture and will be used to make both quad-core and dual-core processors. Different products in the family will target servers, workstations, desktops and laptops, according to the firm.

"We believe that what we have now is the world's first working 45nm processor," said Steve Smith, vice president of Intel's Digital Enterprise Group. He added that working samples of 45nm chips had already run Windows Vista, XP and Mac OS in the lab.

The move from 65nm to 45nm involves more than just a shrink of current chip designs. Intel said the Penryn family will have additional features to enhance performance, such as new SSE4 instructions for accelerating high-performance computing applications.

"Penryn will also have higher clock rates and more cache than 65nm processors," said Smith.

The first 45nm quad-cores will be built using two dual-core chips connected together inside a multi-chip package (MCP), as is the case with Intel's current quad-core processors.

Intel senior fellow Mark Bohr said that the firm's 45nm process uses a combination of new materials, such as hafnium, and is a "significant breakthrough" that allows a doubling of transistor density with a 30 percent reduction in switching power. This will enable forthcoming chips to keep within the existing power envelope of 65nm processors while delivering more performance, Bohr said.

Intel's push to deliver 45nm chips stands in contrast with the strategy of its rival AMD, which has only just begun to introduce 65nm versions of its processors.

However, AMD will ship quad-core products this summer in which all four processors are on a single chip, a design which allows for higher performance than Intel's quick-to-market method of stitching together two dual-core chips, according to AMD.